The present invention relates to a process for fabricating a semiconductor device having a gate-drain overlapped device(GOLD) structure, in particularly a MOS transistor thereof.
Large-scale integration of semiconductor memory devices inevitably calls for an extremely critical design rule upon manufacturing of the unit semiconductor device, even up to sub-micron or less than 0.5 micron for a memory device of several or several tens of mega-bytes. Under such circumstance the reliability of a MOS transistor degrades and its punch-through voltage goes down, thereby involving the entire reconsideration of the operating voltage level and the structure applied thereto. In order to resolve this problem, there has been developed a drain-engineering method. The drain-engineering method employs DDD(Double Diffused Drain) structure having a drain doubly diffused with arsenic and phosphorous (as shown in vol. ED-30, pp 652-657, IEEE transaction of electron devices, 1983), or LDD (Lightly Doped Drain) structure having a drain and a source comprised of a doubly diffused region of a low doping-concentration region and high doping-concentration region (as shown in vol. ED-27, pp 1359-1367, IEEE TED, 1980). Both structures are used to prevent the degradation of the reliability of the semiconductor device. However, the disclosed structures have an inherent limitation in improving the reliability of the devices. This is partly because of the fact that the overlap length between the gate and the drain-source is an important parameter for control of the characteristics of such large-scale integrated devices.
In order to enhance the reliability of the semiconductor devices, there is disclosed a GOLD (gate-drain overlapped device) structure having a gate overlapped over a drain and a source, whose manufacturing method is published in pp 765-772, the articles 1 and 2 of IEDM, 89.
Referring to FIG. 1 illustrating the process for fabricating a conventional LDD type MOS transistor, the gate is an inverted T-shape. The conventional semiconductor devices has a P-well 1 and an N-well 2 for respectively forming an N-type and a P-type MOS transistor. A gate oxide layer 3, a field oxide layer 6 connected to a gate oxide layer 3, a polysilicon layer 4 and a low-temperature oxide(LTO) layer 5 are sequentially formed over the two wells, as shown in FIG. 1A. Contact holes 8, 9 are formed by using a photoresist pattern 7 deposited on the LTO layer 5. Thereafter the contact holes 8, 9 respectively are subjected to an ion-implantation of P-type and N-type impurities, as shown in FIG. 1B. After the ion-implantation, the contact holes 8 and 9 are filled with polysilicon to form polysilicon layers 12, 13. Then, is repeated a process that a selective ion-implantation process is carried out, after sequentially removing the photoresist pattern 7 and the LTO layer 5 and selectively depositing an oxide layer 16. Thereby the low-concentration sources and drains 14,15;17,18 of the NMOS and PMOS transistors are formed, as shown in FIG. 1C. Then the polysilicon layers 4, 12 are patterned to form the inverted T-shape gates 19, 21. Thereafter a thick LTO layer is deposited over the whole surface of the semiconductor substrate, and an etching process for forming gates having side wall oxide layers 20, 22, as shown in FIG. 1D. In this case the remainder of the LTO layer only in the side walls of the polysilicon gates 19, 21. Finally is repeated another process that a selective ion-implantation process is carried out by utilizing the gates comprised of the polysilicon gates 19, 21 and the side wall oxide layers 20, 22, after selectively depositing an oxide layer 25, thus the high-concentration sources and drains 23,24;26,27 of the NMOS and PMOS transistors are formed, as shown in FIG. 1D.
In the above conventional process, although the overlap widths of the low doping-concentration source and drain may be adjusted through controlling the sizes of the inverted T-shape polysilicon gates 19, 21 and side wall oxide layers 20, 22, an additional masking process is required to remove the remainder of the gate oxide layer 3 over the sources and drains in order to form the source/drain-contacts. Namely it is impossible to employ the self-align contact process that does not need an additional masking process.
In the field of fabricating semiconductor devices, it will be easily appreciated by one skilled in the art that the performance of the patterns without an additional masking process directly results in simplification of the processing steps and reduction the number thereof, thus inducing low-production cost.
FIG. 2 illustrates the conventional process of fabricating an LDD type MOS transistor as disclosed in the above article 2 of IEDM, 89. The gate is an oxide-sandwiched inverted T-shape. A poly gate 34 is formed, after sequentially depositing a gate oxide layer 31, a polysilicon layer 32, and an oxide layer 33 over the whole surface of a semiconductor substrate, as shown in FIG. 2A. Next, the impurities are ion-implanted and diffused to form a low-concentration source and drain 35, 36. A polysilicon layer 37 is deposited over the whole surface of the substrate, as shown in FIG. 2B, and covered with a thick dielectric layer (or oxide layer) 38 as shown in FIG. 2C. Then the polysilicon layer 37 and the thick dielectric layer 38 are subjected to an etching process to form a gate as shown in FIG. 2D, wherein the remainder of the thick dielectric layer 38 is only in the side walls of the polysilicon gate of inverted T-shape, and is served as oxide layer spacer 39. Thereafter the ion-implantation and thermal diffusion process are performed to form a high-concentration source and drain 40, 41.
In order to form a contact hole in the gate oxide layer 31 over the source and drain, an additional masking process is required like the method disclosed in the article 1. Namely the self-align process may not be applied to the contact process. Moreover, in the conventional processes illustrated in FIGS. 1 and 2, the overlap widths between the low-concentration source/drain and the inverted T-shaped polysilicon gate, are controlled by the widths of the wing portions (horizontal) of the inverted T-shaped gate and oxide spacer (or side wall oxide layer of FIG. 1) which are formed by etching process. Therefore, it is difficult to obtain a precise control of the overlap widths. For example, referring to FIG. 2, the gate-drain/source overlap widths of the low-concentration source and drain depend upon the process margin for the thickness of the polysilicon layer 37 deposited in the process of FIG. 2B and the process margin for the width of the oxide layer spacer 39 formed in the process of FIG. 2D. Thus the practically formed gate-drain/source overlap widths comprises undesirable error.